PhD Position – Thermal Effects in 3D Integrated Circuits, France

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  The fellowship will be grated throughout the duration of the work, which will take place in a highly dynamic and international field in Grenoble (France). The high requirements on today’s mobile systems push them beyond the limit of a simple communication tool, and make them reminiscent of a global assistance terminal that includes entertainment, office and general services. This translates into a continuous increase in terms of required computational performance. The scaling ability of complementary metal-oxide-semiconductor (CMOS) technology offers one possible way to increase the system performance. However, it comes with a high cost in terms of fabrication complexity and power efficiency. Another alternative that addresses these hurdles consists of vertically staking electronic chips on top of each other using vertical connections (Fig. 1) called the through-silicon vias (TSV), thus increasing the computational performance, while using the same system footprint.

Key competences:

– Knowledge in the field of classical thermal physics – Understanding of solid-state physics and MOS transistors – Ability to carry out physical modelling and numerical simulations using a finite element simulator – Ability to carry out electrical test and characterization and to develop automated data input and processing tools – Basic understanding of CMOS circuits and logic systems – Ability to design basic logic circuits or ability to develop this competence – Required team work within the frame of numerous collaborations with the involved teams – Excellent time management skills – Creativity, self-motivation, personal engagement – Very good academic grade

Deadline: Contact Employer, haykel.ben-jamaa-at-cea.fr

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